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HV9931 HV9931 Unity Power Factor LED Lamp Driver
Features
Constant output current Large step-down ratio Unity power factor Low Input current harmonic distortion Fixed frequency or fixed off-time operation Internal 450V linear regulator Input and output current sensing Input current limit Enable, PWM and phase dimming
General Description
The HV9931 is a fixed frequency PWM controller IC designed to control an LED lamp driver using a single-stage PFC buckboost-buck topology. It can achieve a unity power factor and a very high step-down ratio that enables driving a single high-brightness LED from the 85-264VAC input without a need for a power transformer. This topology allows reducing the filter capacitors and using non-electrolytic capacitors to improve reliability. The HV9931 uses open-loop peak current control to regulate both the input and the output current. This control technique eliminates a need for loop compensation, limits the input inrush current, and is inherently protected from input under-voltage condition. Capacitive isolation protects the LED Lamp from failure of the switching MOSFET. HV9931 provides a low-frequency PWM dimming input that can accept an external control signal with a duty ratio of 0-100% and a frequency of up to a few kilohertz. The PWM dimming capability enables HV9931 phase control solutions that can work with standard wall dimmers.
Applications
Offline LED lamps and fixtures Street lamps Traffic signals Decorative lighting
Typical Application Circuit
D1
VIN
D4
L1
C1
D2
L2
CIN ~AC ~AC RS1 Q1 D3 RS2 VO
+
Rref2
RCS1 Rref1 RT VIN GATE CS1 GND RT PWMD CS2 VDD
RCS2
C2
HV9931
HV9931
Ordering Information
DEVICE HV9931 Package Options 8-Lead SOIC (Narrow Body) HV9931LG-G
-G indicates package is RoHS compliant (`Green')
Absolute Maximum Ratings
Parameter VIN to GND VDD to GND CS1, CS2 to GND PWMD to GND GATE to GND Value -0.5V to +470V -0.3V to +13.5V -0.3V to VDD + 0.3V -0.3V to (VDD + 0.3V) -0.3V to (VDD + 0.3V)
Pin Configuration
VIN
1
8
RT
CS1
2
7
CS2
HV9931
GND
3
6
VDD
Continuous Power Dissipation (TA = +25C)
Also limited by package power dissipation limit, whichever is lower.
GATE
4
8-Lead SOIC (derate 9mW/C above +25C) Operating temperature range Junction temperature Storage temperature range
5
PWMD
900mW -40C to +85C +125C -65C to +150C
8-Lead SOIC
Product Marking
YWW
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
H9931
LLLL
Y = Last Digit of Year Sealed WW = Week Sealed L = Lot Number = "Green" Packaging
8-Lead SOIC
Electrical Characteristics
(The * denotes the specifications which apply over the full operating junction temperature range of -40C < TA < +85C, otherwise the specifications are at TA = 25C, VIN = 12V, unless otherwise noted)
Symbol Input VINDC IINSD
Parameter Input DC supply voltage range* Shut-down mode supply current*
Min 8 -
Typ 0.5
Max 450 1
Units V mA
Conditions DC input voltage PWMD connected to GND, VIN = 12V
Internal Regulator VDD VDD, line VDD, load UVLO UVLO Internally regulated voltage* Line regulation of VDD Load regulation of VDD VDD undervoltage lockout threshold VDD undervoltage lockout hysteresis 7.12 0 0 6.45 7.5 6.7 500 7.88 1 100 6.95 V V mV V mV VIN = 8, IDD(ext) = 0, PWMD = VDD, CGATE = 500pF VIN = 8 - 450V, IDD(ext) = 0, 500pF at GATE; RT = 226k, PWMD = VDD IDD(ext) = 0 - 1mA, 500pF at GATE; RT = 226k, PWMD = VDD VIN rising ---
2
HV9931
Symbol VPWMD(lo) VPWMD(hi) RPWMD GATE VGATE(hi) VGATE(lo) TRISE TFALL TDELAY TBLANK Oscillator FOSC VOFFSET1 VOFFSET2 Initial accuracy 80 100 120 kHz RT = 226K GATE high output voltage* GATE low output voltage* GATE output rise time GATE output fall time Delay from CS trip to GATE Blanking delay VDD-0.3 0 150 30 30 150 215 VDD 0.3 50 50 300 280 V V ns ns ns ns IGATE = 10mA IGATE = -10mA CGATE = 500pF CGATE = 500pF VIN = 12V, VCSI, VCS2 = -100mV VCSI, VCS2 = -100mV Parameter PWMD input low voltage* PWMD input high voltage* PWMD pull-down resistance Min 2.4 50 Typ 100 Max 1.0 150 Units V V k Conditions VIN = 8 - 450V VIN = 8 - 450V VPWMD = 5V
PWM Dimming
Comparators Comparator Input offset voltage* -15 15 mV ---
Functional Block Diagram
VIN
Regulator
7.5V
VDD
CS1
Leading Edge Blanking
S RQ
Osc
RT
GATE
CS2
PWMD
AGND
HV9931
3
HV9931
Typical Performance Characteristics (T
VDD vs. Junction Temperature (LIN = 2mA)
7.7
J
= 25OC, VIN=100V unless otherwise noted)
Blanking Delay vs. Junction Temperature
300
7.65
250
200
TBLANK (ns)
-20 0 20 40 60 80 100 120
7.6
VDD (V)
150
7.55
100
7.5
50
7.45 -40
Junction Tem perature (C)
0 -40
-20
0
20
40
60
80
100
120
Junction Tem perature (C)
Frequency vs. Junction Temperature (RT = 226K)
93
8 7.5
VDD vs. Regulator Current (VIN = 100V)
92
7
Frequency (kHz)
VDD (V)
91
6.5 6 5.5 5
90
89
4.5
88 -40
4
-20
0
20
40
60
80
100
120
0
2
4
6
8
10
12
14
16
18
20
Junction Tem perature (C)
IIN (mA)
Functional Description Power Topology
The HV9931 is optimized to drive Supertex's proprietary single-stage, single-switch, non-isolated topology, cascading an input power factor correction (PFC) buck-boost stage and an output buck converter power stage. This power converter topology offers numerous advantages useful for driving high-brightness light emitting diodes (HB LED). These advantages include unity power factor, low harmonic distortion of the input AC line current, and low output current ripple. The output load is decoupled from the input voltage with a capacitor making the driver inherently failure-safe for the output load. The power converter topology also permits reducing the size of a filter capacitor needed, enabling use of non-electrolytic capacitors. The latter advantage greatly improves reliability of the overall solution.
The HV9931 is a peak current-mode controller that is specifically designed to drive a constant current buckboost-buck power converter. This patent pending control scheme features two identical current sense comparators for detecting negative current signal levels. One of the comparators regulates the output LED current, while the other is used for sensing the input inductor current. The second comparator is mainly responsible for the converter start-up. The control scheme inherently features low inrush current and input under-voltage protection. The HV9931 can operate with programmable constant frequency or constant off-time. In many cases, the constant off-time operating mode is preferred, since it improves line regulation of the output current, reduces voltage stress of the power components and simplifies regulatory EMI compliance. (See Application Note AN-H52.)
4
HV9931
Input Voltage Regulator
The HV9931 can be powered directly from its VIN pin, and takes a voltage from 8V to 450V. When a voltage is applied at the VIN pin, the HV9931 seeks to maintain a constant 7.5V at the VDD pin. The VDD voltage can be also used as a reference for the current sense comparators. The regulator is equipped with an under-voltage protection circuit which shuts off the HV9931 when the voltage at the VDD pin falls below 6.2V. The VDD pin must be bypassed by a low ESR capacitor ( 0.1F) to provide a low impedance path for the high frequency current of the output gate driver. The HV9931 can also be operated by supplying a voltage at the VDD pin greater than the internally regulated voltage. This will turn off the internal linear regulator and the HV9931 will function by drawing power from the external voltage source connected to the VDD pin.
Input and Output Current Feedback
Two current sense comparators are included in the HV9931. Both comparators have their non-inverting inputs internally connected to ground (GND). The CS1 and CS2 inputs are inverting inputs of the comparators. Connecting a resistor divider into either of these inputs from a positive reference voltage and a negative current sense signal programs the current sense threshold of the comparator. The VDD voltage of the HV9931 can be used as the reference voltage. If more accuracy is needed, an external reference voltage can be applied. When either the CS1 or the CS2 pin voltage falls below GND, the GATE pulse is terminated. A leading edge blanking delay of 215ns (typ) is added. The GATE voltage becomes high again upon receiving the next clock pulse of the oscillator circuit. Referring to the Functional Circuit Diagram, the CS2 comparator is responsible for regulating output current. The output LED current can be programmed using the following equation:
PWM Dimming and Wall Dimmer Compatibility
PWM Dimming can be achieved by applying a TTLcompatible square wave signal at the PWMD pin. When the PWMD pin is pulled high, the gate driver is enabled and the circuit operates normally. When the PWMD pin is left open or connected to GND, the gate driver is disabled and the external MOSFET turns off. The HV9931 is designed so that the signal at the PWMD pin inhibits the driver only, and the IC need not go through the entire start-up cycle each time ensuring a quick response time for the output current. The power topology requires little filter capacitance at the output, since the output current of the buck stage is continuous, and since AC line filtering is accomplished through the middle capacitor rather than the output one. Therefore, disabling the HV9931 via its PWMD or VIN pins can interrupt the output LED current in accordance with the phase-controlled voltage waveform of a standard wall dimmer.
RCS 2 =
Io +
1 I L2 2 RREF 2 RS 2 7.5V
where IL2 is the peak-to-peak current ripple in L2. The CS1 comparator limits the current in the input inductor L1. There is no charge in the capacitor C1 upon the start-up of the converter. Therefore, L2 cannot develop the output current, and the HV9931 starts-up in the input current limiting mode. The CS1 current threshold must be programmed such that no input current limiting occurs in normal steady-state operation. The CS1 threshold can be programmed in accordance with a similar equation: I RCS 1 = L1( PK ) RREF 1 RS 1 7.5V where IL1(PK) is the maximum peak current in L1.
MOSFET Gate Driver
Typically, the gate driving capability of the HV9931 is limited by the amount of power dissipation in its linear regulator. Thus, care must be taken selecting a switching MOSFET to be used in the circuit. An optimal trade-off must be found between the gate charge and the on-resistance of the MOSFET to minimize the input regulator current.
Oscillator
Connecting an external resistor from RT pin to GND programs switching frequency: 25000 FS [kHz ] = RT [K ]+ 22 Connecting the resistor from RT pin to GATE programs constant off-time:
TOFF [ s ] =
RT [K ]+ 22 25
5
HV9931
Functional Circuit Diagram
D1
VIN
D4
L1
C1
L2 D2
iL1 CIN ~AC ~AC RS1
+
Q1
VC1
_
D3
iL2 VO RS2
+ _
RCS2
_ VS1 +
RCS1 RT
+
VS2
GATE
PWMD
RT
OSC
SQ R
CS1
CS2
Rref1
Rref2
RE G
VIN VDD GND
HV9931
7.5V
CDD
Switching Waveform
VDD
GATE
0
t
iL2
0
t
iL1
0
t
6
HV9931
Pin Description
Pin # 1 2, 7 3 4 5 Pin Name VIN CS1, CS2 GND GATE PWMD Description This pin is the input of a high voltage regulator. These pins are used to sense the input and output currents of the converter. They are the inverting inputs of the internal comparators. Ground return for all the internal circuitry. This pin must be electrically connected to the ground of the power train. This pin is the output gate driver for an external N-channel power MOSFET. When this pin is pulled to GND, switching of the HV9931 is disabled. When the PWMD pin is released, or external TTL high level is applied to it, switching will resume. This feature is provided for applications that require PWM dimming of the LED lamp. This is a power supply pin for all internal circuits. It must be bypassed with a low ESR capacitor to GND. Oscillator control. A resistor connected between this pin and GND sets the PWM frequency. A resistor connected between this pin and GATE sets the PWM off-time.
6 8
VDD RT
7
HV9931
8-Lead SOIC (Narrow Body) Package Outline (LG)
4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
D 8 E E1
Note 1 (Index Area D/2 x E1/2) L 1
L2
Gauge Plane
1
L1
Seating Plane
Top View A
Note 1
View B View B
h h
A
A2
Seating Plane
A1
e
b
Side View
A View A-A
Note 1: This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol
A
A1
A2
b
D
E
E1
e
h
L
L1
L2
1
MIN Dimension (mm) NOM MAX
1.35 1.75
0.10 0.25
1.25 -
0.31 0.51
4.80 4.90 5.00
5.80 6.00 6.20
3.80 3.90 4.00 1.27 BSC
0.25 0.50
0.40 1.27 1.04 REF 0.25 BSC
0O 8O
5O 15O
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005. Drawings not to scale.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV9931 A042307
8

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